This relates to solid-state image sensors and more specifically, to in sensors with small pixels having high well capacity.
Typical image sensors sense light by converting impinging photons into electrons or holes that are integrated (collected) in sensor pixels. After completion of an integration cycle, collected charge is converted into a voltage, which is supplied to the output terminals of the sensor. In complementary metal oxide semiconductor (CMOS) image sensors, the charge to voltage conversion is accomplished directly in the pixels themselves and the analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes. The analog signal can be also converted on-chip to a digital equivalent before reaching the chip output. The pixels have incorporated in them a buffer amplifier, typically a Source Follower (SF), which drives the sense lines that are connected to the pixels by suitable addressing transistors.
After charge to voltage conversion is completed and the resulting signal transferred out from the pixels, the pixels are reset in order to be ready for accumulation of new charge. In pixels that use a Floating Diffusion (FD) as the charge detection node, the reset is accomplished by turning on a reset transistor that conductively connects the FD node to a voltage reference, which is typically the pixel drain node. This step removes collected charge; however, it also generates kTC-reset noise as is well known in the art. This kTC-reset noise is removed from the signal using a Correlated Double Sampling (CDS) signal processing technique in order to achieve the desired low noise performance. CMOS image sensors that utilize a CDS technique usually include three transistors (3T) or four transistors (4T) in the pixel, one of which serves as the charge transferring (Tx) transistor. It is possible to share some of the pixel circuit transistors among several photodiodes, which also reduces the pixel size. An example of a 4T pixel circuit with pinned photodiode can be found in U.S. Pat. No. 5,625,210 to Lee, incorporated herein as a reference.
FIG. 1 is a simplified cross-sectional view of a portion of a typical image sensor pixel 100. As shown in FIG. 1, image sensor pixel 100 includes a pixel photodiode (PD) that collects the photon-generated carriers, a charge transfer gate 110 of a charge transfer transistor, and a floating diffusion 104. The pixel is fabricated in a substrate 101, that has a p+ doped layer 102 deposited on a back surface. The device substrate 101 also includes an epitaxial p-type doped layer 115 situated above the p+ type doped layer 102. The photons that enter this region generate carriers that are collected in the potential well of the photodiode (PD) formed in region 108.
The surface of epitaxial layer 115 is covered by an oxide layer 109 that isolates the doped poly-silicon charge transfer gate Tx 110 from the substrate. A masking cap oxide 111 is deposited on an upper surface of poly-silicon gate 110, which serves as a patterning hard mask as well as an additional blocking mask for the ion implantation that forms the PD charge storage region. The PD is formed by an n-type doped layer 108 and a p+ type doped potential pinning layer 107.
Sidewall spacers 116 are sometimes incorporated to control the mutual edge positions of p+ type doped layer 107 and charge storage layer 108. The FD diode 104 that senses charge transferred from the PD is connected to the pixel source follower SF transistor (not shown). The FD, SF, and the remaining pixel circuit components are all built in the p-type doped well 103 that diverts photon-generated charge into the photodiode potential well located in layer 108. The pixels are isolated from each other by p+ type doped regions 105 and 106, which may extend all the way to the p+ type doped layer 102. The whole pixel is covered by several inter-level (IL) oxide layers 112 (only one is shown in FIG. 1) that are used for pixel metal wiring and interconnect isolation. The pixel active circuit components are connected to the wiring by metal via plugs 114 deposited through contact holes 113.
Pixel well capacity is determined primarily by the capacitance between p+ doped layer 107 and charge storage layer 108. By increasing the doping levels in these layers, it is possible to achieve close-to-abrupt doping profiles in the vertical direction in these layers and approach the maximum electric field intensity permissible in the silicon before breakdown. Some contribution to charge storage capacitance is also obtained from the capacitance between n-type doped layer 108 and pixel p+ type doped separation layers 105 and 106. However, due to ion implantation doping profile straggle in the lateral direction, it is not generally possible to achieve the same abrupt doping profile characteristic in this direction as in the vertical direction. There is also almost no storage well capacity contribution from the capacitance between layer 108 and substrate p-type epitaxial doping region 115.
Image sensors are being fabricated with smaller and smaller pixels, it is not uncommon for pixels to have sub-micron dimensions. When pixel size is reduced, the area of doping layers 108 and 107 is also reduced, which in turn leads to a loss in well capacity. An improvement in storage well capacity in small size pixels is discussed in U.S. Pat. No. 8,247,853 to Hynecek, which is hereby incorporated by reference herein.
It may therefore be desirable to he able to provide image sensor pixels such as small image sensor pixels (e.g., pixels with sub-micron dimensions) with increased storage well capacity.